RapidIO II IP Core 4x Variations Might Issue Unexpected packet-retry Control Symbol - RapidIO II IP Core 4x Variations Might Issue Unexpected packet-retry Control Symbol Description RapidIO II IP core 4x variations might issue a packet-retry control symbol on the RapidIO link after receiving a small number of consecutive, small RapidIO packets. This issue occurs because the IP core reserves 256 bytes of space, the space required for a maximum-sized packet, for every incoming packet, even if the packet is small. In addition, the IP core requires more time to read a packet from its RX buffer than to write a packet to the RX buffer. When the IP core detects the RX buffer is becoming full, it issues a packet-retry control symbol on the RapidIO link. The IP core does not drop any packets as a result of this issue. However, the issue impacts throughput. This issue occurs after a stream of consecutive, small packets arrive on the RapidIO link. If the IP core receives 256-byte packets, the issue does not occur. Resolution To avoid this issue, ensure the IP core link partner does not send a sequence of consecutive packets with only eight bytes, 16 bytes, or 32 bytes of payload. More specifically, Altera has tested the following data patterns: If all packets have a payload size of 256 bytes followed by an explicit end-of-packet indication (EOP is provided even in the case of back-to-back packets), the issue does not occur. If all packets have payload sizes of 64 bytes, 128 bytes, or 256 bytes, and they are not SWRITE transactions, the issue is less likely to occur. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']