Why do undriven input ports on a module in the golden design cause formal verification mismatches? - Why do undriven input ports on a module in the golden design cause formal verification mismatches? Description This type of mismatch may occur when a port is undriven in the golden design. In this case, Encounter Conformal assigns a "Z" value on the undriven port, but the revised design has a predefined value for that port assigned by the Quartus ® II software. Encounter Conformal detects that the designs are not functionally equivalent and reports a mismatch related to the ports. In some cases, the problem occurs when you use VHDL instantiations of some Altera ® megafunctions. To avoid this problem, generate your megafunction variation in Verilog HDL. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Verification'] ['novalue'] novalue novalue ['Stratix® FPGAs'] ['novalue'] ['novalue'] ['novalue']