Why does the F-Tile System PLL fail to lock when the reference clock is active only after configuration? - Why does the F-Tile System PLL fail to lock when the reference clock is active only after configuration? Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might observe the F-Tile System PLL lock failure when your design has both below requirements: More than one System PLL are enabled in one F-Tile, e.g. syspll0 and syspll1 One System PLL reference clock source will only be active after the other System PLL is locked. E.g. syspll0 refclk is active only after syspll1 is locked. Failure Symptom : The later System PLL will never lock. E.g syspll0 refclk is active only after syspll1 is locked, then syspll0 could never lock. Background : When a System PLL reference clock source is not active at configuration, then all System PLL reference clock must unselect parameter And the F-Tile Reference and System PLL Clocks FPGA IP will expose below control signals for each System PLL: refclock_ready[n] en_refclk_fgt_i Expected behavior : For each System PLL #n, after its reference clock source #i is active, then we can drive refclock_ready[n] and en_refclk_fgt_i to get System PLL #n locked independently from other System PLL. Root Cause : A SSM (Secure Socket Manager) FW bug causes the control signals of the 3 System PLLs can not work independently. Resolution There is no workaround available. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software. Custom Fields values: Troubleshooting QS-192583 novalue ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 26.1 ['Agilex® 7 FPGAs and SoCs']