Creating Reusable Design Blocks: Introduction to IP Reuse with the Altera® Quartus® Prime Software - 18 Minutes This training is part 1 of 3. As FPGA designs get larger and more complicated, intellectual property (IP) is being used more often to help reduce time-to-market. Including IP allows designers to focus on new aspects of their design and improve existing designs instead of spending time recreating what’s been done before. But what if you want to create your own IP? This training is for the IP designer who wants to create high-quality, easily-reusable IP based on Altera's own methodology for designing reusable IP for use in the Altera® Quartus® Prime software. Course Objectives At course completion, you will be able to: Recognize the benefits of reusing existing IP and complete designs Understand what is required to create good reusable IP Skills Required Background in digital logic design Familiarity with an HDL language (Verilog or VHDL) Familiarity with the Altera® Quartus® Prime software Familiarity with Tcl scripting Some familiarity with SDC timing constraints Reference Course Code: If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OIPR1000. FPGA_OIPR1000. <p>Creating Reusable Design Blocks: Introduction to IP Reuse with the Altera Quartus Prime Software</p>