Why does my LVDS interface fail hold timing in Cyclone V 300GT devices in the Fast 0C timing corner? - Why does my LVDS interface fail hold timing in Cyclone V 300GT devices in the Fast 0C timing corner? Description Due to a problem in the Quartus ® II software version 12.0 SP2 and earlier, you may see these timing violations in your Cyclone ® V 300GT design. There is an problem with t he Fast 0C timing model for these devices. Resolution This problem has been fixed beginning with the Quartus II software version 12.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0.2 ['Cyclone® V GT FPGA'] ['novalue'] ['novalue'] ['novalue']