Parretto DisplayPort IP Core - The Parretto DisplayPort is a resource optimized DisplayPort v1.4 IP Core solution for FPGA devices. Designed for easy of use, the core is available as both source (DPTX) and sink (DPRX). Microtronix is a full service product development company offering an integrated suite of hardware and software design services tailored to delivering 4K UHD SDI video overlay product solutions for… Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA The DisplayPort IP-core is a DisplayPort 1.4 solution for FPGA implementation. It has a resource optimized footprint and it is written in SystemVerilog. A thin host driver comes with the IP-core. The application software controls the IP-core through this driver. Support for 1, 2 and 4 DP lanes in RBR, HBR, HBR2 and HBR3 line rates. Color depth is 8-bits and color space is RGB 4:4:4. Audio / Video Broadcast Medical Parretto DisplayPort IP Core Key Features DisplayPort TX (DPTX) - SST Offering Brief No No No Yes C/C++ Verilog Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA No No 23.2.0 Offering Brief Production a1JUi0000049UJEMA2 What's Included IP-core is available as both source (DPTX) and sink (DPRX) Ordering Information 5311-00-00 a1JUi0000049UJEMA2 Production Intellectual Property (IP) a1MUi00000BO8seMAD a1MUi00000BO8seMAD Select 2026-01-30T05:03:09.000+0000 The Parretto DisplayPort is a resource optimized DisplayPort v1.4 IP Core solution for FPGA devices. Designed for easy of use, the core is available as both source (DPTX) and sink (DPRX). Partner Solutions