Error(175001): The Fitter cannot place 1 LVDS_CHANNEL, which is within LVDS SERDES Intel FPGA IP - Error(175001): The Fitter cannot place 1 LVDS_CHANNEL, which is within LVDS SERDES Intel FPGA IP Description You may get this error when the LVDS SERDES Intel® FPGA IP transmitter is driven by a PLL from adjacent I/O banks in intel® Arria® 10 devices. The Intel® Quartus® Prime Pro Edition Software does not allow I/O PLLs to drive transmitter channels in adjacent I/O banks. This will result in additional jitter on TX channels caused by the clock path traversing the core / cascaded PLLs. Resolution If an I/O bank PLL drives transmitter channels in adjacent I/O banks, it must drive at least one transmitter channel in the same bank. The Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook will be updated to emphasize the LVDS placement guideline as shown below: The I/O bank PLL can drive the differential transmitter channels in an adjacent I/O bank only in the following conditions: The interface is a wide LVDS SERDES Intel® FPGA IP transmitter interface that spans multiple I/O banks With tx_outclock enabled —the transmitter has more than 22 channels With tx_outclock disabled —the transmitter has more than 23 channels The PLL also drives at least one transmitter channel in its own I/O bank Custom Fields values: ['novalue'] Troubleshooting 15013243546 False ['novalue'] ['novalue'] novalue novalue ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']