Error (175006): Could not find path between the IOPLL and destination LVDS_CHANNEL - Error (175006): Could not find path between the IOPLL and destination LVDS_CHANNEL Description You may see this error message in Arria® 10 when an LVDS IOPLL clock is being driven across multiple banks. In Arria 10 it is illegal for GCLKs to drive across multiple banks. Resolution The Triple Speed Ethernet (TSE) LVDS variant supports up to 11 ports per instance if placed within a single bank. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']