Warning: Node: reconfig_clk[0] was determined to be a clock but was found without an associated clock assignment. - Warning: Node: reconfig_clk[0] was determined to be a clock but was found without an associated clock assignment. Description You might see this warning during the fitter and static timing analysis stages in the Intel® Quartus® Prime Software version 17.0 when compiling a design with the JESD204B standalone IP core targeting an Intel® Arria® 10 device, due to the fact that that the reconfig_clk is unconstrained in the IP. Resolution To work around this problem, define the reconfig_clk in the IP SDC file at frequency 100 MHz - 125 MHz. This problem is fixed starting from the Intel Quartus Prime Software version 17.0.1. Custom Fields values: ['novalue'] Troubleshooting FB: 464960; False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 17.0.1 17.0 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-10