Why does the F-Tile PMA/FEC Direct PHY IP variant with:“PMA type” set “FGT”, “Datapath clocking mode” set “PMA”, “PMA width” set "16” “Enable TX and RX double width transfer” disabled, fail to pass Quartus “Support Logic Generation”? - Why does the F-Tile PMA/FEC Direct PHY IP variant with:“PMA type” set “FGT”, “Datapath clocking mode” set “PMA”, “PMA width” set "16” “Enable TX and RX double width transfer” disabled, fail to pass Quartus “Support Logic Generation”? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile PMA/FEC Direct PHY IP variant with the “ PMA type ” parameter set to “ FGT ”, the “ Datapath clocking mode ” set to “ PMA ”, the “ PMA width ” parameter set to “ 16 ”, the “ Enable TX double width transfer ” parameter disabled , and the “ Enable RX double width transfer ” parameter disabled , will fail to pass Quartus “Support Logic Generation” if the IP is using the 200G Hard IP block of the F-Tile. The errors that are generated will contain a string that is similar to the ones shown below: Error (21843): Rule: gdrb_gdr_e200g_top::e200g_stream0_rx_excvr_if_fifo_mode_rule @ gdr.z1577b.u_e200g_top Error (21843): (gdr.z1577b.u_e200g_top.e200g_25g_0_rx_en -> u0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx.rx_en) == FALSE || (gdr.z1577b.u_e200g_top.e200g_25g_0_rx_excvr_if_fifo_mode -> u0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx.rx_excvr_if_fifo_mode) != E200G_25G_0_RX_EXCVR_IF_FIFO_MODE_REGISTER || gdr.z1577b.u_e200g_top.e200g_stream0_rx_excvr_if_fifo_mode == E200G_STREAM0_RX_EXCVR_IF_FIFO_MODE_REGISTER Error (21843): Rule: gdrb_gdr_e200g_top::e200g_stream0_rx_primary_use_rule @ gdr.z1577b.u_e200g_top Error (21843): (gdr.z1577b.u_e200g_top.e200g_25g_0_rx_en -> u0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx.rx_en) == FALSE || (gdr.z1577b.u_e200g_top.e200g_25g_0_rx_primary_use -> u0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx.rx_primary_use) != E200G_25G_0_RX_PRIMARY_USE_DIRECT_BUNDLE || gdr.z1577b.u_e200g_top.e200g_stream0_rx_primary_use == E200G_STREAM0_RX_PRIMARY_USE_DIRECT_BUNDLE Error (21843): Rule: gdrb_gdr_e200g_top::e200g_stream0_rx_xcvr_width_rule @ gdr.z1577b.u_e200g_top Error (21843): (gdr.z1577b.u_e200g_top.e200g_25g_0_rx_en -> u0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx.rx_en) == FALSE || (gdr.z1577b.u_e200g_top.e200g_25g_0_rx_xcvr_width -> u0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx.rx_xcvr_width) != E200G_25G_0_RX_XCVR_WIDTH_16 || gdr.z1577b.u_e200g_top.e200g_stream0_rx_xcvr_width == E200G_STREAM0_RX_XCVR_WIDTH_16 Error (21843): Rule: gdrb_gdr_e200g_top::e200g_stream0_sys_clk_src_rule @ gdr.z1577b.u_e200g_top Resolution To work around this problem, you could ensure that the IP variant uses the 400G Hard IP block by choosing pin assignments for your design that allow placement with the 400G Hard IP. Alternatively, you could ensure that your IP variant is using the 400G Hard IP block by adding a Quartus Settings File(QSF) assignment to your project, similar to the one shown below. Note that the hierarchy will be specific to your design. set_instance_assignment -name IP_BB_LOCATION -to u_0|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx EHIP400G This problem was fixed in version 24.3.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16025079224 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.3 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']