Error: Fractional PLL parameter 'mimic_fbclk_type' is set to an illegal value of 'none' on node >name< - Error: Fractional PLL parameter 'mimic_fbclk_type' is set to an illegal value of 'none' on node >name< Description You may get this error if the Quartus® II IP (qip) file that is generated by the Altera_PLL megafunction is not being referenced during Quartus II compilation. This .qip file contains the required feedback clock assignment and without it, you will see this error. Resolution Add the .qip file generated by the Altera_PLL megafunction to your project, by going to the Project menu in the Quartus II software and select Add/Remove Files in Project... Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']