Why are the Intel® FPGA HDMI IP Core Trailing Scrambled Data Island Guardbands For Channel 1 & 2 Not Encoded Correctly? - Why are the Intel® FPGA HDMI IP Core Trailing Scrambled Data Island Guardbands For Channel 1 & 2 Not Encoded Correctly? Description When using the Intel® FPGA HDMI IP core for HDMI TX 2.0 operation, errors will be observed for channel 1 and 2 if the attached HDMI sink implements character error detection. This is due to the data island trailing guardbands for channel 1 and 2 not being TMDS encoded correctly. The Intel FPGA HDMI IP Core TX module does not ensure "cnt" track data stream disparity during the data island periods, which violates the HDMI 2.0 specification. This problem should have no impact to the video display. Resolution There is no workaround for this problem. This problem is fixed in Intel® Quartus® version 16.1 update 1 of the Intel FPGA HDMI IP core. Custom Fields values: ['novalue'] Troubleshooting FB: 412054; True ['HDMI IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.1.1 15.0 ['Arria® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']