Lossless and Lossy CCSDS 122.0-B-1 Encoder - CCSDS-122-E Alma Technologies designs, markets, sells and supports high-quality, innovative and feature-rich semiconductor IP products since 2001. A certified Quality Management System in line with the EN ISO… Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The CCSDS-122-E encoder IP core from Alma Technologies is a complete and self-contained implementation of the CCSDS 122.0-B-1 image data compression standard. It offers numerically lossless or Lossy image data compression with up to 16-bit pixel dynamic range. The encoder accepts the uncompressed image data in standard raster-scan pixel order and outputs standalone and fully compliant CCSDS 122.0-B-1 byte-stream format. The CCSDS-122-E is designed for enabling high-rate data compression with low silicon resource usage and without needing an external memory device for its operation. It is available for Altera FPGA and SoC based designs. The CCSDS 122.0-B-1 standard was developed to balance between compression performance and complexity. Similar to JPEG 2000, it utilizes a two-dimensional Discrete Wavelet Transform (DWT) for image data decorrelation. CCSDS 122.0-B-1 uses a 9/7 integer DWT for the lossless compression, while a 9/7 float DWT is also specified for improved lossy compression efficiency, especially at low bit-rates. Both DWT options are available by the CCSDS-122-E core. For complete control by the application of the lossy compression ratio, the CCSDS-122-E includes also the optional rate control functionality that is provisioned by the standard. The CCSDS-122-E is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. It is a complete and autonomous encoder, not needing any host system CPU or GPU support for its operation. Being carefully designed and rigorously verified, the CCSDS-122-E is a reliable and easy-to-use and integrate IP core. Video and Image Processing Aerospace Defense Home Audio/Video Lossless and Lossy CCSDS 122.0-B-1 Encoder Key Features Full compliance to the CCSDS 122.0-B-1 specification Offering Brief No No No No VHDL Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® V GS FPGA Stratix® V GX FPGA No Yes 24.3.1 Offering Brief Production a1JUi0000049U5iMAE What's Included Pre-synthesized and verified Netlist for FPGA and SoC devices Ordering Information CCSDS-122-E a1JUi0000049U5iMAE Production Intellectual Property (IP) a1MUi00000BO8r9MAD a1MUi00000BO8r9MAD Select 2026-04-21T12:58:28.000+0000 CCSDS-122-E Partner Solutions