Programming Support Center - The Programming Center provides an explanation of the programming solutions for the FPGA programmable MAX® II, MAX® 3000A, MAX® 7000 and Configuration Devices. The Programming Center provides an explanation of the programming solutions for the MAX® II, MAX® 3000A, MAX® 7000 and Configuration Devices. Design Pages {"title":"Programming Support Center"} Programming Tools Adapters and Download Cables FPGA devices can be programmed with FPGA programming tools, and download cables. Download Cable Driver Information Programming Adapters Information In-Circuit Tester In-circuit testers are widely used for manufacturing tests and for the measurement of PCB systems. Using In-Circuit Testers to Program ISP-Capable Devices Boundary-Scan Tools You can use boundary-scan tools to program and verify programmable logic devices (PLDs) that support in-system programmability (ISP) that utilizes the IEEE Standard 1149.1 controller. Using Boundary-Scan Tools to Program ISP-Capable Devices Third-Party Programmers Third-party vendors offer support for programming MAX® 3000A devices. Support for Third-Party Programming Hardware IEEE 1532 Programming Third-party vendors offer programming support for configuration devices. IEEE 1532 Programming Jam STAPL The Jam Standard Test and Programming Language (STAPL) was created by FPGA engineers and is supported by a consortium of programmable logic device (PLD) manufacturers, programming equipment makers, and test equipment manufacturers. Jam STAPL was adopted as JEDEC standard JESD-71 in August, 1999. ISP & the Jam STAPL Programming Support for Jam STAPL Language Pin-Out Files Pin-Out Files for FPGAs Programming Tools Configuration Device The EPC and EPCS configuration device product families are discontinued. Please refer to PDN 1708 for more details. Configuration Device FPGA enhanced configuration devices (EPC16, EPC8, and EPC4) and serial configuration devices (EPCS4, EPCS1, EPCS16, and EPCS64) offer a cost-effective configuration solution for all FPGA. The enhanced and serial configuration devices have different programming methods as described below. Enhanced Configuration Device Programming Methods FPGA enhanced configuration devices (EPC16, EPC8, and EPC4) and serial configuration devices (EPCS4, EPCS1, EPCS16, and EPCS64) offer a cost-effective configuration solution for all FPGAs. The enhanced and serial configuration devices have different programming methods as described below. Enhanced configuration (EPC) devices can be programmed in-system via the industry standard 4-pin IEEE Standard 1149.1 (JTAG) interface. Serial Configuration Device Programming Methods The serial configuration (EPCS) devices do not support the JTAG interface, the conventional method to program these devices is via the active serial (AS) programming interface. The EPCS devices can be programmed using the following methods: In-System Programming Using External Microprocessor EPCS devices can be programmed in-system by an external microprocessor using SRunner. SRunner is a software driver developed for embedded serial configuration device programming that designers can customize to fit in different embedded systems. SRunner (ZIP) In-System Programming Using Serial Flash Loader EPCS devices can be programmed via the JTAG interface by using an FPGA as a bridge between the JTAG interface and the EPCS device. AN 370: Using the FPGA Serial Flash Loader with the Quartus® Prime Software MAX® II Devices Documentation Using Jam STAPL for ISP via an Embedded Processor chapter of the MAX® II Device Handbook MAX® II CPLDs Support FPGA Knowledge Base Articles Do I have to reprogram my MAX® II device if I want to use a different VCCIO voltage level for a bank? MAX® II Devices MAX® 7000S, MAX® 7000A, and MAX® 7000B Devices Documentation Enhanced Configuration Devices Data Sheet Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet FPGA Knowledge Base Articles Can I program FPGA ISP devices concurrently (MAX® and EPC families)? Are there internal oscillators in FPGA EPC devices? What input file should be used to program an EPCS device? How many times can I program and erase the serial configuration devices (EPCS1 and EPCS4)? How can I erase an FPGA device in-system using the JTAG pins? Why do MAX® 7000A, MAX® 7000AE, MAX® 7000S, and MAX® 9000 device programming times vary depending on whether I use a master programming unit (MPU), a PC, or a programmer? Can I program FPGA in-system programmable (ISP) devices concurrently (MAX® and EPC families)? MAX® 7000S, MAX® 7000A, and MAX® 7000B Devices MAX® 7000 Devices Documentation MAX® 7000 Programmable Logic Device Family Data Sheet AN 95: In-System Programmability in MAX® Devices AN 109: Using the HP 3070 Tester for In-System Programming FPGA Knowledge Base Articles Can I interrupt the programming of a MAX® 7000AE, MAX® 7000B, or MAX® 3000A device without damaging it? Is there any way to monitor the ISP DONE bit (MAX® 7000AE, MAX® 7000B, MAX® 3000A)? Are the Programmer Object Files (.pof) within the MAX® 7000 device family (MAX® 7000E, MAX® 7000S, and MAX® 7000A) compatible? Can I program the four JTAG pins (TCK, TMS, TDI, and TDO) as I/O pins when programming MAX® 7000 devices via a third-party socket-based programmer? MAX® 7000 Devices MAX® 3000 Devices Documentation MAX® 3000A Programmable Logic Device Family Data Sheet AN 95: In-System Programmability in MAX® Devices AN 109: Using the HP 3070 Tester for In-System Programming Knowledge Base Can I interrupt the programming of a MAX® 7000AE, MAX® 7000B, or MAX 3000A device without damaging it? Is there any way to monitor the ISP DONE bit (MAX® 7000AE, MAX® 7000B, MAX® 3000A)? What is the status of the I/O pins on an unprogrammed MAX® 3000A, 7000S, 7000A, 7000B, and MAX® II device? MAX® 3000 Devices Related Links FPGA Software Download Center MAX® II handbook JTAG Configuration Boundry-scan (BSDL) Support Related Links