Why does the MIPI link fail despite successful FPGA reconfiguration (Phase 2) in HPS First boot mode on Agilex™ 5 or Agilex™ 3 SoC FPGAs? - Why does the MIPI link fail despite successful FPGA reconfiguration (Phase 2) in HPS First boot mode on Agilex™ 5 or Agilex™ 3 SoC FPGAs? Description For HPS First Agilex™ 5 or Agilex™ 3 SoC FPGAs designs that include shared IO in the HPS EMIF banks, a firmware problem may cause the MIPI link to fail. This is due to the shared IO potentially getting stuck in reset after FPGA reconfiguration (Phase 2). This failure is not observed for FPGA First designs or designs that do not use shared IO. Refer to 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) or A.1.13.1. Restrictions on I/O Bank Usage for Agilex™ 3 EMIF IP with HPS for more information regarding IO sharing. Resolution This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15017556275; 15017727280 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']