Error: rs232_0: The input clock frequency must be known at generation time. - Error: rs232_0: The input clock frequency must be known at generation time. Description Due to a problem in the Quartus® Prime Standard Edition Software v18.0 and earlier, you may see this error message when generating the HDL design file for an RS232 UART IP in IP Parameter Editor. Resolution To work around this problem, add an RS232 UART instance from IP Catalog in Platform Designer. Custom Fields values: ['novalue'] Troubleshooting 2205674200 False ['RS232 UART IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 18.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']