Altera® FPGA E-Tile Clocking - 28 Minutes This online course will introduce the clocking resources found in Altera® Agilex ® F-Series and Altera® Stratix® 10 MX/TX/DX FPGA E-Tiles. In this course, you will learn about the reference clocks available on the E-tile. Then, you will learn how the E-tile transceiver datapath clocks are generated and distributed. Finally, you will learn how the E-tile transceiver clocks must be connected at the FPGA fabric interface. The goal of the course is to help you understand your use of clocking resources, which can be key to a successful design implementation. Course Objectives At course completion, you will be able to: Describe the clock resources of the Altera® Agilex ® F-Series and Altera® Stratix® 10 FPGA MX/TX/DX E-Tiles Correctly connect the FPGA interface clocks to the E-tile to avoid compilation and timing errors Skills Required Understanding of the Ethernet protocols, particularly 10G, 25G and 100G Ethernet Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus Prime design software Familiarity with Altera® FPGA E-Tile architecture OR viewing the following course: "Altera® FPGA E-Tile Transceiver Basics" If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OETILECLK. FPGA_OETILECLK. <p>Altera FPGA E-Tile Clocking</p>