Remote System Upgrade for MAX 10 FPGA - Remote System Upgrade for MAX 10 FPGA 「AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor」の「Figure 1. Reference Design Block Diagram」では、NiosⅡを使用してDual Configuration IP Core を制御しておりますが、、NiosⅡとDual Configuration IP CoreのCLK周波数はちがってもよろしいですか。使用しているFPGAは、10M16SCE144C8Gです。 NiosⅡのCLK = 50MHz Dual Configuration IP CoreのCLK = 40MHz Replies: Re: Remote System Upgrade for MAX 10 FPGA Thank you for your reply. Replies: Re: Remote System Upgrade for MAX 10 FPGA Hi YSuzu21, We use the same clock for NIOS II and Dual Configuration IP. we use similar PLL output to these NIOS II IP and Dual Configuration IP: Cheers