Why can't I pack my second pipeline register of sload signal into the DSP Block when inferring the mult_accum functionality? - Why can't I pack my second pipeline register of sload signal into the DSP Block when inferring the mult_accum functionality? Description When the customer infers the mult_accum module, they will find that the second pipeline register of the sload signal cannot be packed into the DSP Block. This will affect timing analysis results. Resolution To work around this issue, use the ALTMULT_ACCUM MegaCore® to preform the register packing. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V FPGAs and SoCs', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']