Why do I get three unconstrained clocks in the Timing Analyzer for my DDR3 controller in Arria® V devices? - Why do I get three unconstrained clocks in the Timing Analyzer for my DDR3 controller in Arria® V devices? Description Due to a problem in the Quartus® II software version 12.0sp2 and later, three unconstrained clocks might appear in the Timing Analyzer when creating a DDR3 controller with UniPHY for Arria® V ST, GX, and GT devices. The clock output pin names end with the following: <hierarchy>|dqs_enable_ctrl~DFFEXTENDDQSENABLE Resolution These unconstrained clocks can safely be ignored. This problem has been fixed in the Intel® Quartus® Prime Edition Software version 13.1. Custom Fields values: ['novalue'] Troubleshooting 2205800903 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 12.0.2 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA'] ['novalue'] ['novalue'] ['novalue']