Why is the PCI Express Hard IP not generating ECRC when Advanced error reporting (AER), ECRC checking, ECRC generation and ECRC forwarding are enabled? - Why is the PCI Express Hard IP not generating ECRC when Advanced error reporting (AER), ECRC checking, ECRC generation and ECRC forwarding are enabled? Description The PCI® Express Hard IP will not automatically set the TLP TD bit if ECRC forwarding is enabled. When ECRC forwarding is enabled the TLP TD bit will be sent unchanged by the IP. You should ensure that the Avalon Streaming (Avalon-ST) header has the TD bit set. If ECRC forwarding is not enabled and ECRC generation is enabled, the core will automatically set the TLP TD bit and generate the ECRC. Resolution To automatically set the TLP TD bit in the transmitted header, disable the ECRC forwarding. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']