Why do the GTS HDMI FPGA IP, GTS SDI II FPGA IP, and GTS DisplayPort PHY FPGA IP fail to compile when the RX and TX are combined in Dual Simplex mode with an empty TX channel? - Why do the GTS HDMI FPGA IP, GTS SDI II FPGA IP, and GTS DisplayPort PHY FPGA IP fail to compile when the RX and TX are combined in Dual Simplex mode with an empty TX channel? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, when using the Agilex™ 5 devices in Dual Simplex configuration mode, the RX channel must not be paired to an empty TX channel, or a compilation error will be caused. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15016394631 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']