Altera® FPGAs Timing Analysis: Lecture - This instructor-led class is taught in a virtual classroom over 1 half day of instruction. This class consists of presentation only, along with the chance to ask questions of the instructor throughout the presentation. To get practice using what you have learned, sign up for the Timing Analysis: Hands-on Lab class. Course Description You will learn how to constrain & analyze a design for timing using the Timing Analyzer in the Quartus® Prime Pro software v. 22.1. This includes writing Synopsys* Design Constraint (SDC) files, generating various timing reports in the Timing Analyzer, and applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the Timing Analyzer makes it easy to create timing constraints to help you meet those requirements. Note: While the focus of this course is the Quartus Prime Pro software, most of the flow and constraints are valid with the Standard and Lite versions of the software. Course Objectives At course completion, you will be able to: Understand the Timing Analyzer timing analysis design flow Apply basic and intermediate timing constraints to an FPGA design Analyze an FPGA design for timing using the Timing Analyzer Skills Required Completion of the instructor-led course Beginner Workshop for Altera® FPGAs OR completion of the eLearning Quartus Curriculum series OR a working knowledge of the Quartus Prime software Understanding of basic hardware timing parameters and equations used in the timing verification OR completion of the eLearning Understanding Timing Analysis in FPGAs If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_IDSW122. FPGA_IDSW122. <p>Altera FPGAs Timing Analysis: Lecture </p>