Why does the Stratix® V Hard IP for PCI Express fail to complete DMA transactions when using the Descriptor Controller interface? - Why does the Stratix® V Hard IP for PCI Express fail to complete DMA transactions when using the Descriptor Controller interface? Description Due to a problem with the Descriptor Controller IP, simultaneous DMA read-and-write operations with the Stratix® V Hard IP for PCI Express for Avalon® Memory-Mapped Interface with DMA core might stop DMA transaction before completion. Resolution To work around the problem, after a whole DMA read completes, start a DMA write (or, after a whole DMA write completes, start a DMA read). This problem is fixed in Quartus® software version 14.0. Custom Fields values: ['novalue'] Troubleshooting 1408044213 False ['DMA'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.1 ['Stratix® V FPGAs', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']