Error(15744): ( topology != EHIP_4CH_PTP_FEC ) in Intel® Quartus® Prime Software version 19.4 and earlier - Error(15744): ( topology != EHIP_4CH_PTP_FEC ) in Intel® Quartus® Prime Software version 19.4 and earlier Description Due to a bug in the Intel® Quartus® Prime Software version 19.4 and earlier, you may see the following Intel® Quartus® Prime Fitter if instantiating two copies of the Intel E-Tile Hard IP for Ethernet Intel FPGA IP in Intel Stratix® 10 and Intel Agilex® 7 FPGA E-Tile transceiver devices. Error(15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct illegal pin assignments, and recompile your design. Error(15744): In atom <path>|alt_ehipc3_0|alt_ehipc3_hard_inst|EHIP_CORE.c3_ehip_core_inst' Error(15744): The settings must match one or more of these conditions: Error(15744): ( topology != EHIP_4CH_PTP_FEC ) You may see this error when the two Intel E-Tile Hard IPs for Ethernet are configured for 100GbE with PTP and RSFEC enabled, and are constrained to adjacent PTP blocks. For example: Two Intel E-Tile Hard IP for Ethernet configured for 100GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_0 and EHIP_CORE_1 may fail to fit Two Intel E-Tile Hard IP for Ethernet configured for 100GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_2 and EHIP_CORE_3 may fail to fit Two Intel E-Tile Hard IP for Ethernet configured for 100GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_0 and EHIP_CORE_2 may fit Two Intel E-Tile Hard IP for Ethernet configured for 100GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_1 and EHIP_CORE_3 may fit Resolution This problem is fixed in Intel® Quartus® Prime Software version 20.1 and later. Custom Fields values: ['novalue'] Troubleshooting 1307432879 False ['Stratix® 10 E-Tile Transceiver Native PHY'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 19.4 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']