Memory Controller Uses 1T Memory Timing - Memory Controller Uses 1T Memory Timing Description Version 11.0 and later of the high-performance controller II (HPC II) uses 1T memory timing, even in half-rate designs; 1T memory timing can reduce address and command margins, especially for designs targeting DIMMs. You should ensure that your board designs are sufficiently robust to maintain the memory clock rising edge within the 1T address-command window.You can use the Additional address and command clock phase option on the PHY Settings tab of the parameter editor to adjust the phase of the address and command if necessary. Resolution There is no workaround for this issue. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']