Nios-V alt_epcq_controller_write() Problem - Nios-V alt_epcq_controller_write() Problem Hi, I have a flash on my custom board which is MT25QU01G. The flash is connected to Nios-V/g with Epcq Controller. I am trying to erase, write, read sectors from flash. Before write and erase I unlock all sectors and after write and erase I lock all sectors. The problem is that my alt_epcq_controller_write() returns success(0) however it doesn't write to flash memory. I read same data from same place and it is not changed. I also look that memory from memory browser and still nothing changed. I call erase method before each write method since it is nor flash but nothing happens. Could you please help me about the problem. Thanks, Balerion Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi ShoH, Thanks for your response. I will be using that. Balerion Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi Balerion, Regading to avl_mem slave: If you also place avl_mem slave in Peripheral Region, you can use the current altera_epcq_controller.c file as is. However, you may want to place avl_mem slave in cacheable (non-Peripheral) region to take advantage of the cache for read accesses. In that case, cache maintenance needed for flash memory write operation in Nios V/g system. Here is a code example (= not fully validated) to achieve this attached (please replace the file extension from ".txt" to ".c"). At the end of the alt_epcq_controller_write_block() function, cache flush function call and error checking are added. Thanks, ShoH Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi Balerion, In any case, it is highly recommended to use non-cached access to Peripherals in order to ensure reliable and stable access to Peripherals. Thanks, ShoH Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi ShoH, Before I try what you suggest I did another thing which is I used to call Public API's in order like: For write operation: alt_epcq_controller_lock(); // with related params to unlock all sectors alt_epcq_controller_write(); // with related params to erase and write alt_epcq_controller_lock(); // with related params to lock all sectors I was doing that for every write operation. then what I did is when initializing I'm opening the lock of all sector once then don't deal with any locking: alt_epcq_controller_lock(); // with related params to unlock all sectors SleepMs(20); For Write operation: alt_epcq_controller_write(); // with related params to erase and write It seems, this solved my problem. I did some tests like writing and reading different size of data and comparing them none of them failed. Thanks for help, Balerion Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi Balerion, Yes, disable caching(0Kilobytes of cache) is another option and a good choice when you use Tightly Coupled Memories(TCMs). (In my design, I usually disable cache when I can use sufficient size of TCMs.) There is no difference between Peripheral A and Peripheral B for the core. You may use ether one. When you feel convenient with two separeate peripheral region, you can use both. These allow you to use separate regions for Peripheral. Accessing TCM always bypasses cache memory(=Cache is never used for TCM accesses). So you don't need to worry about peripheral region for TCM. https://www.intel.com/content/www/us/en/docs/programmable/683632/25-3/accessing-tightly-coupled-memory.html "peripheral access must be non-cached" : Caches store copies of data, and accessing peripheral registers through a cache can result in reading "stale" data, or a write could be held in the cache and never write to the peripheral hardware. Please note that this is due to the way CPU caches work and is not specific to Nios V. Please let me know if disabling cache or caring peripheral region helps to resolve the QSPI access issue. Thanks, ShoH Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi ShoH, So, what I understand up to now is that there are two options for me. The first one is that I will disable caching in my nios-v/g configuration(0Kilobytes of cache) and the other option is that according to "https://www.intel.com/content/www/us/en/docs/programmable/726952/25-1/memory-configurations-tab.html" I have to place my peripherals to non-cached address space to do that I need to create peripheral region. There comes a few questions to my mind: What differs between Peripheral A and Peripheral B and which one should I choose? Let's say I create peripheral region, Do I need to also create tightly coupled memory region as well or peripheral region is enough? Why do peripherals have to be located to the non-cached address space? Thanks, Balerion Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi Balerion, Thanks for checking. OK, I need to say: You must locate registers of peripheral IPs in a peripheral region. https://www.intel.com/content/www/us/en/docs/programmable/726952/25-1/peripheral-region.html If the jtag uart appears to work within your current system, please consider it a coincidence. At a minimum, in your system, you must define a Peripheral Region to place the jtag uart and the epcq avl_csr registers in peripheral region, such like: Peripheral Region Size : 64 KBytes or larger Peripheral Region Base Address : 0x48050000 Thanks, Sho Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi, I looked at memory configuration page and see that my Data cache and Instruction cache sizes are 4KiloBytes. All my Peripheral regions and Tightly coupled memory settings are 0. My jtag uart base address is 0x48050060. I am able to use jtag uart without a problem. Is there anything you want me to check? Thanks, Balerion Replies: Re: Nios-V alt_epcq_controller_write() Problem I see that you are using Serial Flash Controller. Cached and non-cached regions( = peripheral regions) are specified in your HW design (Nios V IP configuration in PlatformDesigner). If the HW design was not designed by you, please check with your HW designer. (I think UART or JTAG-UART is used in your design and the UART works as expected. If so, the UART registers should already be correctly located in a peripheral region. ) https://www.intel.com/content/www/us/en/docs/programmable/726952/25-1/memory-configurations-tab.html Regards, Sho Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi, I am using Serial Flash Controller such that the generated bsp includes "altera_epcq_controller.h" It would include "altera_epcq_controller2.h" if I use Serial Flash Controller II as much as I know. Could you please tell me how to look for the cached and non-cached addresses . My ram starts from base address 0x00000000 to 0x3FFFFFFF and my epcq flash avl memory starts from base address 0x40000000 and my avl csr base starts from 0x48050040. I don't know which addresses are cached or not. Thanks, Balerion Replies: Re: Nios-V alt_epcq_controller_write() Problem Thanks for the info. I'll check if I can prepare a similar set-up. Regarding flash controller, are you using Serilal Flash Controller, not Serial Flash Controller II ? And just to be sure, you are assigning avl_csr address of the flash controller in non-cached address region, right? Regards, Sho Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi, I'm using Quartus Pro 25.1.1 and My Fpga is Arria-10. Thanks, Balerion Replies: Re: Nios-V alt_epcq_controller_write() Problem Hi Balerion I'll try to reproduce the issue. Can you share Quartus version and FPGA device that you are using with? Regards, Sho