Why cant I use a transceiver recovered clock to feed a transmitter PLL reference clock on Altera transceiver devices? - Why cant I use a transceiver recovered clock to feed a transmitter PLL reference clock on Altera transceiver devices? Description The Quartus® II Software will deliberately prevent you from connecting a recovered clock from a receiver to the reference clock input of a transmitter PLL. The recovered clock is extracted from the clock embedded in the received datastream. As the datastream has propagated across a channel, the recovered clock will have undefined jitter characteristics which if fed into the reference clock of a transmitter PLL, may cause the transmit jitter to exceed a given protocols' transmit jitter specification. The recommended method of implementing a recovered clock synchronous architecture is to route the recovered clock outside of the FPGA, and to pass the clock through a jitter cleaner before routing back onto the FPGA through one of the dedicated transceiver reference clock pins. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Stratix® II GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']