External Memory Interfaces in Agilex™ FPGAs (Part 4): On-Chip Debugging - Same Course in Simplified Chinese: Altera® Agilex®器件中的存储器接口片上调试 Same Course in Japanese: インテル Agilex™ デバイスのメモリー・インターフェイスのオンチップデバッグ 66 Minutes This training is part 4 of 4. Altera® Agilex™ FPGAs introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR5 running at up to 5.6 Gbps on some devices. This part of the training discusses the use of tools for debugging a memory interface during runtime: the EMIF Debug Toolkit, the On-Chip Debug Port, the Efficiency and Performance Monitors, Traffic Generator 2.0, and the Test Engine IP. The EMIF Debug Toolkit provides runtime information through a JTAG connection or through software control on the calibration and available margin in a memory interface. The Traffic Generator and Test Engine IP let you create and send custom data patterns to the memory for post-calibration tests. Due to the changes in implementation from previous devices, this training also discusses what is required to use these tools with designs that include multiple memory interfaces. Course Objectives At course completion, you will be able to: Perform on-chip debugging of a memory interface using the EMIF Debug Toolkit Generate custom traffic patterns for testing using Traffic Generator 2.0 or the Test Engine IP Analyze interface efficiency and identify bottlenecks using the Efficiency or Performance Monitor IP Skills Required Background in digital logic design Basic knowledge of memory interfaces and their implementation in Altera® FPGA devices Familiarity with the Altera® Quartus® Prime software If the audio for the course does not start automatically, press pause and then play on the course player. A transcript of the course audio is available in the Notes or closed captioning (cc) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OAGMEM104. FPGA_OAGMEM104. <p>External Memory Interfaces in Agilex FPGAs (Part 4): On-Chip Debugging</p>