Why does the ALTECC decoder simulation have glitches when the parity bit is incorrect? - Why does the ALTECC decoder simulation have glitches when the parity bit is incorrect? Description In the Quartus® II software version 12.1 SP1 and later, on the output of the ALTECC decoder megafunction you may see glitches on the parity bit for all single-bit errors. Resolution To work around this problem, add one pipeline stage on the decoding result by setting output latency of 1 clock cycle in ALTECC wizard. Custom Fields values: ['novalue'] Troubleshooting 1408175884 False ['IP Turbo Encoder/Decoder IP-TURBO'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']