Does the Stratix V Hard IP for PCI Express support Gen3 Phase 2 and Phase 3 equalization in simulation? - Does the Stratix V Hard IP for PCI Express support Gen3 Phase 2 and Phase 3 equalization in simulation? Description The auto generated Stratix ® V Hard IP for PCI Express ® test bench Root Port bus functional model (BFM) bypasses Gen3 Phase 2 and Phase 3 Equalization. If using a third-party Root Port BFM, modify it to terminate Equalization after Phase 0 and Phase 1 have completed. Resolution Custom Fields values: ['novalue'] Troubleshooting novalue False ['PCI Express', 'Simulation'] ['novalue'] novalue novalue ['Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']