Why does Triple-Speed Ethernet Intel® FPGA IP fail for 10M/100M speeds when MAC is configured for 8-bit FIFO? - Why does Triple-Speed Ethernet Intel® FPGA IP fail for 10M/100M speeds when MAC is configured for 8-bit FIFO? Description Due to problem in the transmitter of the Triple-Speed Ethernet Intel® FPGA IP and the F-Tile Triple-Speed Ethernet Intel® FPGA IP, the design fails when the MAC only variant is configured for an 8-bit FIFO. Resolution This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 23.1. Custom Fields values: ['novalue'] Troubleshooting 16016559360 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.2 ['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'MAX® 10 10 FPGAs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']