Timing Violations in CPRI MegaCore Function for Some Device Families, Speed Grades, and Line Rates - Timing Violations in CPRI MegaCore Function for Some Device Families, Speed Grades, and Line Rates Description Timing violations may occur in CPRI MegaCore functions that target the following combinations of device family, speed grade, and CPRI line rate: CPRI line rate 6144 Mbps targeting an Arria II GX speed grade I3 device CPRI line rate 3072 Mbps targeting a Cyclone IV GX speed grade I7 or C7 device In the affected variations, data might be lost on TX PLD_PCS paths in the CPRI MegaCore function. Resolution To avoid this issue, demote the TX PCS clock tx_clkout from a periphery or global clock to a LAB clock, by adding the following line to the Quartus II Project Settings File ( .qsf ) before compilation: set_instance_assignment -name GLOBAL_SIGNAL OFF -to <variation>*tx_clkout* This issue will not be fixed in a future version of the CPRI MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Basic Functions Clocks (Primary)'] ['FPGA Dev Tools Quartus II Software'] novalue 9.1.2 ['Arria® II FPGAs', 'Arria® II GX FPGA', 'Cyclone® IV FPGAs'] ['novalue'] ['novalue'] ['novalue']