Why do I see a performance drop if the TLP length is less than 64B when using Scalable Switch Intel® FPGA IP for PCI Express*? - Why do I see a performance drop if the TLP length is less than 64B when using Scalable Switch Intel® FPGA IP for PCI Express*? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.2 and earlier, you might see a performance drop if the TLP length is less than 64B when using Scalable Switch Intel® FPGA IP for PCI Express*. Resolution This problem is not planned to be fixed in future releases of the Intel® Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting 15014033381 False ['P-Tile Switch for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix No plan to fix ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']