Why do I see hold time violations in Triple Speed Ethernet IP Core with Quartus II v15.0? - Why do I see hold time violations in Triple Speed Ethernet IP Core with Quartus II v15.0? Description Due to a problem in Quartus® II software version 15.0, you may see marginal hold time violation especially in multi-channel Triple Speed Ethernet IP Core designs that target Arria® V, Arria® 10 , Cyclone® V and Stratix® V device families. Resolution To work around this issue, add the following Synopsys Design Constraint file ( .sdc ) constraints for Fitter into your project SDC file. if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } { set_min_delay -from [get_keepers {*<tse_entity_name>*}] -to [get_keepers {*<tse_entity_name>*}] 0.0ns } else { set_min_delay -from [get_keepers {*<tse_entity_name>*}] -to [get_keepers {*<tse_entity_name>*}] <value> } *Note: Increase the “<value>” from “0.1ns” to “0.2ns” if the hold time violation persisted. Refer to “Table 2-2: Recommended Quartus II Pin Assignments” in Triple-Speed Ethernet MegaCore Function User Guide for other related recommendations. For TSE IP with IEEE 1588v2 feature enabled and target Arria V device family, apply the following patch in addition to the workaround above: Please download the appropriate Quartus® II software version 15.0 patch 0.14 from the following links: Download the version 15.0 patch 0.14 for Windows (.exe) Download the version 15.0 patch 0.14 for Linux (.run) Download the Readme for the Quartus II software version 15.0 patch 0.14 (.txt) This is scheduled to be fixed in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']