Signal Tap Logic Analyzer: Introduction & Getting Started - 47 Minutes This training is part 1 of 4. The Signal Tap embedded logic analyzer (ELA) is a system-level debugging tool that monitors the state of internal FPGA design signals and triggers on custom, user-defined conditions during run-time operation of the device without having to bring signals out to device I/O pins. It integrates directly into your design, making it easy to perform functional debug. This part of the training introduces you to the ELA and its many features. You'll also learn about the Signal Tap debugging process flow and how to get started using the tool. Use this training as a Quick Start guide for debugging your designs. Course Objectives At course completion, you will be able to: Understand the basic debugging flow for using the Signal Tap ELA with an FPGA design Add one or more instances of the signal Tap logic analyzer to a design Tap design signals for monitoring and for building trigger conditions Skills Required Basic knowledge of the Altera® Quartus® Prime software Knowledge of external logic analyzer operations (optional) If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODSW1164. FPGA_ODSW1164. <p>Signal Tap Logic Analyzer: Introduction & Getting Started</p>