Is the supported range for Control Bits (CS) in the JESD204C Intel® FPGA IP correct? - Is the supported range for Control Bits (CS) in the JESD204C Intel® FPGA IP correct? Description Due to a known problem in Intel® Quartus® Prime Pro software version 19.4 and earlier, the JESD204C Intel® FPGA IP has a Control Bits (CS) range of 0 - 31. However the supported range is 0 - 3. Resolution Select Control Bits (CS) within 0 - 3 range when using the JESD204C Intel® FPGA IP. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1. Custom Fields values: ['novalue'] Troubleshooting 1507475443 False ['JESD'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.2 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 7 FPGA F-Series', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']