Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Cyclone® V devices? - Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Cyclone® V devices? Description When implementing the OBSAI protocol using the Deterministic Latency PHY in Cyclone® V devices, you may fail to achieve rx_syncstatus when IDLE, IDLE_ACK, and IDLE_REQ patterns are sent during the link-up process. You can achieve synchronization by retriggering rx_patternalign or asserting rx_digitalreset. Resolution This applies to the Deterministic Latency PHY with the following configuration. Data Rate: 3.072 Gbps PMA-PCS Data Width: 20-bits Related Articles Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Arria V GX/GT devices? Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Arria V GZ and Stratix V devices? Custom Fields values: ['novalue'] Troubleshooting 2205972129 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix No plan to fix ['Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']