altera scfifo ip with power-up initial value - altera scfifo ip with power-up initial value in the quartus 25.3 with agilex7, I can see the retiming restriction about scfifo power-up initial value in the retiming rpt. from the altera user guide, the scfifo sclr must be asserted by user logic during power-up, so can I enable the setting ignore_power_up_initial_value to fix retiming restriction without any side effect? Replies: Re: altera scfifo ip with power-up initial value I believe this is a duplicate of the case discussed here: https://community.altera.com/discussions/quartus-prime/retiming-issue/353167 Please continue the discussion in that thread for better tracking. Regards, Richard Tan Replies: Re: altera scfifo ip with power-up initial value Yeah，we never use the initial power up condition in the rtl code. But we need to instantiate the scfifo IP, and the scfifo IP shows the retiming restriction about power-up initial value, not our user logic. I have added the setting for scfifo ip. set_instance_assignment –name IGNORE_REGISTER_POWER_UP_INITIALIZATION ON –to <instance name> Will enabling this configuration together with synchronous reset affect the normal operation of the FIFO? Replies: Re: altera scfifo ip with power-up initial value We recommend not to use initial power up conditions for Hyperflex Architecture. Resets should be used to put the chip into a known state. If initial power-up conditions must be used, then we recommend that clocks be gated to prevent race conditions and functional errors by using the Reset Release IP. If you verify that removing such initial conditions is functionally correct, you can specify the following .qsf assignment to remove those initial conditions: set_instance_assignment –name IGNORE_REGISTER_POWER_UP_INITIALIZATION ON –to <instance name> Please checkout the user guide below for further details: https://docs.altera.com/r/docs/683353/25.1.1/hyperflex-architecture-high-performance-design-handbook/initial-conditions-and-retiming Regards, Richard Tan