Why do I get "min_pulse_width" timing violations on my 1588/PTP 10/25G E-tile Hard IP for Ethernet Intel® FPGA IP core? - Why do I get "min_pulse_width" timing violations on my 1588/PTP 10/25G E-tile Hard IP for Ethernet Intel® FPGA IP core?
Description Due to a problem in the Intel® Quartus® Prime Software version 18.0.1, you might see "min_pulse_width" timing violations in the 10/25G 1588/PTP E-tile Hard IP for Ethernet Intel® FPGA IP core. Resolution There is no workaround for this issue. This issue is fixed in the Intel® Quartus® Prime Software version 18.1.
Custom Fields values:
['novalue']
Troubleshooting
FB: 569078;
True
['Ethernet']
['FPGA Dev Tools Quartus® Prime Software Pro']
18.1
18.0.1
['Stratix® 10 TX FPGA']
['novalue']
['novalue']
['novalue'] - 2023-01-23
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