Error Occurs When Running Simulation Example Design in ModelSim or Riviera-PRO - Error Occurs When Running Simulation Example Design in ModelSim or Riviera-PRO Description When you attempt to run the UniPHY simulation example design in ModelSim or Riviera-PRO, you may receive the following error: Error: (vsim-125) The shared library ./submodules/libbytestream_pli.so being loaded was built on a 32-bit machine. A 32-bit shared library cannot be loaded in a 64-bit simulation. Please use compatible machines to build and load the library This issue affects DDR2 and DDR3 protocols, and QDR II/II and RLDRAM II when using the Nios II-based sequencer. Resolution There are two possible workarounds for this issue: Use a 32-bit version of the ModelSim or Riviera-PRO executable. In a text editor, open msim_setup.tcl under < variant_name > _example_design/simulation/verilog/mentor/ or < variant_name > _example_design/simulation/vhdl/mentor/ . Locate the alias elab section and remove -pli /submodules/libbytestream_pli.so from the vsim line. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']