Why are the core_clk_out timing constraints for PCI Express interfaces for Cyclone® IV GX devices ignored by the Quartus® II software. - Why are the core_clk_out timing constraints for PCI Express interfaces for Cyclone® IV GX devices ignored by the Quartus® II software. Description Due to a problem in the Quartus® II software version 9.1 SP1 and earlier, for Cyclone® IV GX devices the auto-generated core_clk_out SDC constraint is made incorrectly and the following warning will be generated during the Analysis and Sythesis stage. Warning: Ignored assignment: create_clock -name {core_clk_out} -period 8.000 -waveform { 0.000 4.000 } [get_nets {*altpcie_hip_pipen1b_inst|core_clk_out~clkctrl}] Warning: Argument <targets> is an empty collection To work around this problem, change the core_clk_out SDC constraint in the <variation name>.sdc file to: create_clock -name {core_clk_out} -period 8.000 [get_nets *altpcie_hip_pipen1b_inst|core_clk_out*] Resolution This problem is not scheduled to be fixed in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting 2205708662 False ['Generic Component'] ['novalue'] novalue novalue ['Cyclone® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']