Do I have to drive both ports of a differential a pin in gate level simulation netlists or do I need to provide a true differential input? - Do I have to drive both ports of a differential a pin in gate level simulation netlists or do I need to provide a true differential input? Description If your top level design in the Quartus® II software instances Altera differential IO buffers or uses IP blocks with top level differential inputs ( p and n ports at the top level) your external logic must drive a true differential signal into the Quartus II generated netlist. If an Altera Differential IO buffer model sees an unbalanced input it will drive X onto the output. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']