Quartus II Simulation Vector File Not Generated - Quartus II Simulation Vector File Not Generated
Description FIR Compiler does not create a vector file for Quartus II simulation. This issue affects all configurations. The design can be compiled, but there is no automatically generated vector file testbench available to simulate the design in the Quartus II software. Resolution Use NativeLink to simulate the VHDL testbench instead.
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
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10.0
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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