Why does the Intel® Quartus® Prime Pro Edition Software fail to perform Simplex User Avalon Memory-Mapped Interface merging while using F-Tile IPs? - Why does the Intel® Quartus® Prime Pro Edition Software fail to perform Simplex User Avalon Memory-Mapped Interface merging while using F-Tile IPs? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, the Simplex Avalon Memory-Mapped Interface merging of Local User Avalon Memory-Mapped Interface does not work in F-Tile IPs. This affects the F-Tile PMA/FEC Direct PHY Intel FPGA IP and should also affect any other F-Tile IPs supporting simplex mode. Resolution Users who are trying to use two simplex IPs in the same hardware location should only enable Avalon Memory-Mapped Interface on one side, not the other. They can use that single enabled port to control Avalon Memory-Mapped Interface for both TX and RX. Custom Fields values: ['novalue'] Troubleshooting 14014242543, 14014242386 True ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.4 21.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']