LDPC IP - The Low-Density Parity-Check (LDPC) IP Core is a high-throughput, low-latency forward error correction (FEC) engine designed to meet the rigorous requirements of next-generation communication and… Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA LDPC IP (Low-Density Parity-Check Intellectual Property) is a high-performance forward error correction (FEC) solution designed to significantly improve data reliability in high-speed digital communication systems. The IP core implements advanced LDPC encoding and decoding algorithms that detect and correct transmission errors caused by noise, interference, or signal degradation. It supports configurable code rates, block lengths, and throughput options, enabling flexible integration into FPGA or ASIC-based systems. The LDPC IP is optimized for low latency, efficient hardware utilization, and high data throughput, making it suitable for applications such as satellite communications, wireless networks, broadband systems, and next-generation communication standards. Its scalable architecture allows seamless adaptation to different system requirements while maintaining robust error-correction performance. Error Correction Aerospace Defense Government Test Wireless LDPC IP Key Features Ultra-High Throughput: Achieves data rates exceeding multi-Gbps in parallel decoder configurations, with scalability for even higher throughput. Offering Brief No No No Yes Encrypted Verilog Verilog Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi000007eTs5MAE What's Included Synthesizable RTL source code Ordering Information QBL-IP-FEC-LDPC a1JUi000007eTs5MAE Production Intellectual Property (IP) a1MUi00000BOWpkMAH a1MUi00000BOWpkMAH Member 2026-03-10T21:04:28.000+0000 The Low-Density Parity-Check (LDPC) IP Core is a high-throughput, low-latency forward error correction (FEC) engine designed to meet the rigorous requirements of next-generation communication and data storage systems. LDPC codes are known for their near-Shannon limit performance and are widely adopted in standards such as 5G NR, Wi-Fi 6/7, DVB-S2/S2X, G.hn, 10GBASE-T Ethernet, SATA, NVMe, and more. Partner Solutions