Why is SmartVID shown as an VCCL_HPS option for the Hard Processor System Stratix® 10 FPGA IP on Stratix® 10 SoC Low Power devices? - Why is SmartVID shown as an VCCL_HPS option for the Hard Processor System Stratix® 10 FPGA IP on Stratix® 10 SoC Low Power devices? Description Due to a problem in the Quartus® Prime Pro Edition Software version 18.1, the IP parameter editor GUI incorrectly shows the SmartVID option for VCCL_HPS on Hard Processor System Stratix® 10 FPGA IP ->Internal Clocks and Output Clocks ->VCCL_HPS Value. The Stratix® 10 SoC Low Power device(-L) doesn’t support SmartVID. Resolution To work around the problem, select 0.9V or 0.94V in the Hard Processor System Stratix® 10 FPGA IP -> Internal Clocks and Output Clocks ->VCCL_HPS Value option, when using the Stratix® 10 SoC Low Power device. Custom Fields values: ['novalue'] Troubleshooting 2205694201 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']