Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/dap/dap_flr_wrapper.cpp, Line: 1726 - Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/dap/dap_flr_wrapper.cpp, Line: 1726 Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier, you may see this error when compiling a design which contains multiple non-rectangular LogicLock regions. Resolution This problem has been fixed beginning with version 23.1 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14019686197 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ FPGA Portfolio', 'Stratix® FPGAs'] ['novalue'] ['novalue'] ['novalue']