Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/cluster_greedy.c, Line: 3682 - Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/cluster_greedy.c, Line: 3682 Description Due to a problem in the Quartus® Prime Standard Edition Software version 18.1, you may see this internal error when compiling a design that instantiates one or more Clock Control Blocks(ALTCLKCTRL). This problem occurs when targeting Cyclone® V devices. Resolution To work around this error, remove the Clock Control Blocks(ALTCLKCTRL) from the design and fit the design automatically. This problem is fixed starting with the Quartus® Prime Standard Edition Software version 19.1. Custom Fields values: ['novalue'] Troubleshooting 1507266730 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 18.1 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']