Why does FPGA configuration (Phase 2) fail in HPS first boot mode on Agilex™ 7 SoC FPGAs? - Why does FPGA configuration (Phase 2) fail in HPS first boot mode on Agilex™ 7 SoC FPGAs? Description Due to a known problem on Agilex™ 7 SoC FPFAs, FPGA configuration from HPS or Phase 2 configuration may fail if Phase 1 and Phase 2 bitstreams are generated from different design versions compiled with the same version of Quartus® Prime Pro Software. This is due to a mismatch between the HPS IO hash generated during compilation. In HPS's first boot mode, the .sof files used to generate Phase 1 and Phase 2 bitstreams must be compatible to successfully perform Phase 2 configuration. This compatibility is defined by having identical HPS IO and HPS DDR configurations. To ensure the HPS IO and HPS DDR configuration is identical across Quartus designs, you must ensure the following configuration is unchanged between compiles. Resolution To work around this problem, could you make sure that the configuration of the HPS IO and HPS DDR is unchanged between compiles? The following resources contribute to the HPS IO hash calculation : A. When using HPS EMIF on Agilex™ 7 SoC FPGAs : HPS EMIF configuration (placement, routing, and parameter settings) non-HPS EMIF IPs placed in HPS shared GPIO banks (PHYLite, LVDS, MIPI, GPIO, PLL, Calibration IP, etc.) Pin location differences Unconstrained non-HPS EMIF PLLs in HPS shared GPIO banks Differences in register packing in components located in HPS shared GPIO banks B. When using HPS EMIF and NOC on Agilex™ 7 SoC FPGAs M-Series, the following resources from the top horizontal NOC are relevant : NOC PLL HPS shared GPIO banks All AXI4-Lite data You can use the following workarounds to ensure the clock resources on HPS shared GPIO banks remains unchanged between compiles. QSF : set_instance_assignment -name CLOCK_SPINE <numer> -to <clock name> OR INI: pll_clock_spine_in_fpp=<int> to set the default CLOCK SPINE value. Example : A. For clock resources of HPS EMIF PLL to remain unchanged between compiles: set_instance_assignment -name CLOCK_SPINE 31 -to soc_inst|emif_hps|altera_emif_fm_hps_inst|arch|arch_inst|pll_inst|pll_inst B. If a non-HPS PLL is placed in the HPS shared GPIO bank: set_instance_assignment -name CLOCK_SPINE 8 -to fpga_clk_100[0] C. Add to quartus.ini: pll_clock_spine_in_fpp=31 The Agilex™ 7 SoC Boot User Guide is scheduled to be updated with this information. This problem is planned to be fixed in a later release of Quartus® Prime Pro. Related Articles Other causes of a mismatch in HPS IO hash can be found under : Why does FPGA configuration from HPS fail if there are unassigned IOs in an Agilex™ 7 SoC FPGA design ? Why do I see different HPS IO hashes on SDM-based FPGA designs with HPS First boot mode where the HPS EMIF IP is not instantiated? Custom Fields values: ['novalue'] Troubleshooting 18040403942; 18040207384 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.3.1 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']